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dc.contributor.authorSteven, F.L.
dc.contributor.authorAdams, R.G.
dc.contributor.authorSteven, G.B.
dc.contributor.authorWang, L.
dc.contributor.authorWhale, D.
dc.date.accessioned2009-07-27T08:33:59Z
dc.date.available2009-07-27T08:33:59Z
dc.date.issued1993
dc.identifier.citationSteven , F L , Adams , R G , Steven , G B , Wang , L & Whale , D 1993 , ' Addressing Mechanisms for VLIW and Superscalar Processors ' , Microprocessing and Microprogramming , vol. 39 , no. 2-5 , pp. 75-78 . https://doi.org/10.1016/0165-6074(93)90060-X
dc.identifier.issn0165-6074
dc.identifier.otherPURE: 99563
dc.identifier.otherPURE UUID: 1167b328-28b0-4ac4-81a1-5b4698953093
dc.identifier.otherdspace: 2299/3721
dc.identifier.otherScopus: 0027845358
dc.identifier.urihttp://hdl.handle.net/2299/3721
dc.descriptionOriginal article can be found at: http://www.sciencedirect.com/science/journal/01656074 Copyright Elsevier B.V. DOI: 10.1016/0165-6074(93)90060-X [Full text of this article is not available in the UHRA]
dc.description.abstractRISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further simplifying the addressing modes. In particular, the distinctive ORed indexing addressing mechanism employed by the HARP VLIW processor boosts performance by 10%. Register indirect addressing on its own yields a similar performance improvement.en
dc.language.isoeng
dc.relation.ispartofMicroprocessing and Microprogramming
dc.titleAddressing Mechanisms for VLIW and Superscalar Processorsen
dc.contributor.institutionSchool of Computer Science
dc.contributor.institutionCentre for Computer Science and Informatics Research
dc.description.statusPeer reviewed
rioxxterms.versionofrecordhttps://doi.org/10.1016/0165-6074(93)90060-X
rioxxterms.typeJournal Article/Review
herts.preservation.rarelyaccessedtrue


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