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HARP: a statically scheduled multiple-instruction-issue architecture and its compiler
(University of Hertfordshire, 1994)
This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in ...
Static Instruction Scheduling for the HARP Multiple-Instruction-Issue Architecture
(1993)
HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ...
Addressing Mechanisms for VLIW and Superscalar Processors
(1993)
RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further ...
Static instruction scheduling for the HARP multiple-instruction-issue architecture
(University of Hertfordshire, 1992)
HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ...
iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features
(1992)
RISC (Reduced Instruction Set Computers) processors have established an impressive performance standard by executing one instruction in each processor cycle. More recently, VLIW (Very Long Instruction Word) and superscalar ...
A Parallel Pipelined Processor with Conditional Instruction Execution
(1991)
In a recent paper by Smith, Lam and Horowitz [1] the concept of 'boosting' was introduced, where instructions from one of the possible instruction streams following a conditional branch were scheduled by the compiler for ...
The development of iHARP: a multiple instruction issue processor chip
(Institute of Electrical and Electronics Engineers (IEEE), 1991)
During the last decade RISC ideas on processor architecture have become widely accepted. RISC architectures achieve significant performance advantages over CISC architectures by striving to execute one instruction per ...
HARP: a VLIW RISC processor
(Institute of Electrical and Electronics Engineers (IEEE), 1991)
HARP (The Hatfield Risc Processor) is a reduced instruction set processor being developed at Hatfield Polytechnic, UK. The major aim of the HARP project is to develop a VLIW (Very Long Instruction Word) RISC (Reduced ...