Search
Now showing items 1-2 of 2
Static Instruction Scheduling for the HARP Multiple-Instruction-Issue Architecture
(1993)
HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ...
Addressing Mechanisms for VLIW and Superscalar Processors
(1993)
RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further ...