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dc.contributor.authorXu, D L
dc.contributor.authorSotudeh, R
dc.contributor.editorZinterhof, P
dc.contributor.editorVajtersic, M
dc.contributor.editorUhl, A
dc.identifier.citationXu , D L & Sotudeh , R 1999 , A flexible VLSI parallel processing system for block-matching motion estimation in low bit-rate video coding applications . in P Zinterhof , M Vajtersic & A Uhl (eds) , Parallel Computation . vol. 1557/1999 , Lecture Notes in Computer Science , vol. 1557/1999 , Springer , Berlin , pp. 257-264 .
dc.identifier.otherPURE: 445069
dc.identifier.otherPURE UUID: 21865bbd-5327-4879-8b1d-73e2466fcd5f
dc.identifier.otherWOS: 000083635900024
dc.identifier.otherScopus: 0033040227
dc.description“The original publication is available at” Copyright Springer [Full text of this article is not available in the UHRA]
dc.description.abstractIn this paper, we design a flexible VLSI-based parallel processing system for an improved three-step search (ITSS) motion estimation algorithm that is superior to the existing three-step search (TSS) algorithm in all cases and also to the recently proposed new three-step search (NTSS) algorithm if used for low bit-rate video coding, as with the H.261 standard. Based on a VLSI tree processor and an FPGA addressing circuit, the proposed architecture can successfully implement the ITSS algorithm on silicon with the minimum number of gates. Because of the flexibility of the architecture, it can also be extended to implement other three-step search algorithms.en
dc.relation.ispartofParallel Computation
dc.relation.ispartofseriesLecture Notes in Computer Science
dc.titleA flexible VLSI parallel processing system for block-matching motion estimation in low bit-rate video coding applicationsen
dc.contributor.institutionSchool of Engineering and Technology

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