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dc.contributor.authorHe, Y.
dc.contributor.authorSun, Y.
dc.date.accessioned2011-11-22T10:01:21Z
dc.date.available2011-11-22T10:01:21Z
dc.date.issued2001
dc.identifier.citationHe , Y & Sun , Y 2001 , Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm . in Procs IEEE Int Symposium on Circuits & Systems : ISCAS 2001 . vol. 4 , IEEE , pp. 854-857 . https://doi.org/10.1109/ISCAS.2001.922372
dc.identifier.isbn0-7803-6685-9
dc.identifier.otherPURE: 457073
dc.identifier.otherPURE UUID: 1974da70-818e-4e45-b597-9eaa9ba1a641
dc.identifier.otherdspace: 2299/4765
dc.identifier.otherScopus: 0038748768
dc.identifier.urihttp://hdl.handle.net/2299/7072
dc.description“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.”
dc.description.abstractThis paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper.en
dc.language.isoeng
dc.publisherIEEE
dc.relation.ispartofProcs IEEE Int Symposium on Circuits & Systems
dc.rightsOpen
dc.titleFault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-normen
dc.contributor.institutionSchool of Engineering and Technology
dc.contributor.institutionSchool of Engineering and Computer Science
dc.contributor.institutionDepartment of Engineering and Technology
dc.contributor.institutionCentre for Engineering Research
dc.contributor.institutionCommunications and Intelligent Systems
dc.relation.schoolSchool of Engineering and Technology
dc.relation.schoolSchool of Engineering and Computer Science
dc.description.versiontypeFinal Published version
dcterms.dateAccepted2001
rioxxterms.versionVoR
rioxxterms.versionofrecordhttps://doi.org/10.1109/ISCAS.2001.922372
rioxxterms.typeOther
herts.preservation.rarelyaccessedtrue
herts.rights.accesstypeOpen


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