| dc.contributor.author | He, Y. | |
| dc.contributor.author | Sun, Y. | |
| dc.date.accessioned | 2011-11-22T10:01:21Z | |
| dc.date.available | 2011-11-22T10:01:21Z | |
| dc.date.issued | 2001 | |
| dc.identifier.citation | He , Y & Sun , Y 2001 , Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm . in Procs IEEE Int Symposium on Circuits & Systems : ISCAS 2001 . vol. 4 , Institute of Electrical and Electronics Engineers (IEEE) , pp. 854-857 . https://doi.org/10.1109/ISCAS.2001.922372 | |
| dc.identifier.isbn | 0-7803-6685-9 | |
| dc.identifier.other | dspace: 2299/4765 | |
| dc.identifier.uri | http://hdl.handle.net/2299/7072 | |
| dc.description | “This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author's copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder." “Copyright IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.” | |
| dc.description.abstract | This paper deals with fault isolation in nonlinear analog circuits with tolerance under an insufficient number of independent voltage measurements. A neural network-based L1-norm optimization approach is proposed and utilized in locating the most likely faulty elements in nonlinear circuits. The validity of the proposed method is verified by both extensive computer simulations and practical examples. One simulation example is presented in the paper. | en |
| dc.format.extent | 289541 | |
| dc.language.iso | eng | |
| dc.publisher | Institute of Electrical and Electronics Engineers (IEEE) | |
| dc.relation.ispartof | Procs IEEE Int Symposium on Circuits & Systems | |
| dc.title | Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm | en |
| dc.contributor.institution | School of Engineering and Technology | |
| dc.contributor.institution | School of Physics, Engineering & Computer Science | |
| dc.contributor.institution | Department of Engineering and Technology | |
| dc.contributor.institution | Centre for Engineering Research | |
| dc.contributor.institution | Communications and Intelligent Systems | |
| dc.contributor.institution | Centre for Future Societies Research | |
| rioxxterms.versionofrecord | 10.1109/ISCAS.2001.922372 | |
| rioxxterms.type | Other | |
| herts.preservation.rarelyaccessed | true | |
