Browsing by Author "Steven, F.L."

Now showing items 1-12 of 12

    • Adding static data dependence collapsing to a high-performance instruction scheduler 

      Steven, F.L.; Egan, C.; Potter, R.; Steven, G.B. (2001)
      State-of-the-art processors achieve high performance by executing multiple instructions in parallel. However, the parallel execution of instructions is ultimately limited by true data dependencies between individual ...

    • Addressing Mechanisms for VLIW and Superscalar Processors 

      Steven, F.L.; Adams, R.G.; Steven, G.B.; Wang, L.; Whale, D. (1993)
      RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further ...

    • Delayed branches versus dynamic branch prediction in a high-performance superscalar architecture 

      Egan, C.; Steven, F.L.; Steven, G.B. (Institute of Electrical and Electronics Engineers (IEEE), 1997)
      While delayed branch mechanisms were popular with the designers of RISC processors, most superscalar processors deploy dynamic branch prediction to minimise run-time branch penalties. We propose a generalised branch delay ...

    • Dynamic branch prediction using neural networks 

      Steven, G.B.; Anguera, R.; Egan, C.; Steven, F.L.; Vintan, L. (Institute of Electrical and Electronics Engineers (IEEE), 2001)
      Dynamic branch prediction in high-performance processors is a specific instance of a general time series prediction problem that occurs in many areas of science. In contrast, most branch prediction research focuses on ...

    • An evaluation of the architectural features of the iHARP processor 

      Steven, F.L.; Steven, G.B.; Wang, L. (University of Hertfordshire, 1993)
      RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle requires multiple ...

    • An evaluation of the HARP ORed indexing addressing mechanism 

      Steven, F.L. (University of Hertfordshire, 1993)
      Several different adressing mechanisms are evaluated within the context of VLIW and superscalar processor design. The results suggest that traditional RISC addressing mechanisms are less effective than the other simpler ...

    • An evaluation of the iHARP multiple instruction issue processor 

      Steven, F.L.; Steven, G.B.; Wang, L. (University of Hertfordshire, 1994)
      RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue ...

    • An introduction to the Hatfield superscalar architecture 

      Steven, G.B.; Christianson, B.; Collins, R.; Potter, R.; Steven, F.L. (University of Hertfordshire, 1996)
      If a high-performance superscalar processor is to realise its full potential, the complier must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent ...

    • An introduction to the Hatfield Superscalar Scheduler 

      Steven, F.L. (University of Hertfordshire, 1998)
      This document presents a comprehensive overview of the Hatfield Superscalar Scheduler (HSS). It concentrates on the concepts involved rather than on the detailed coding because the scheduler is in a state of evolution and ...

    • A superscalar architecture to exploit instruction level parallelism 

      Steven, G.B.; Christianson, B.; Collins, R.; Steven, F.L.; Potter, R. (1997-03-17)
      If a high-performance superscalar processor is to realise its full potential, the compiler must re-order or schedule the object code at compile time. This scheduling creates groups of adjacent instructions that are independent ...

    • Two-level branch prediction using neural networks 

      Egan, C.; Steven, G.B.; Quick, P.; Anguera, R.; Steven, F.L.; Vintan, L. (2003)
      Dynamic branch prediction in high-performance processors is a specific instance of a general time series prediction problem that occurs in many areas of science. Most branch prediction research focuses on two-level adaptive ...

    • Using a resource limited instruction scheduler to evaluate the iHARP processor 

      Steven, F.L.; Steven, G.B.; Wang, L. (University of Hertfordshire, 1994)
      RISC processors have approached an execution rate of one instruction per cycle by using pipelining to speed up execution. However, to achieve an execution rate of more than one instruction per cycle, processors must issue ...