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Now showing items 11-20 of 23
Artificial evolution: modelling the development of the retina
(University of Hertfordshire, 1996)
The evolution of neural systems relies on the repeated modification of developmental programmes contained within genes. This paper proposes that to efficiently investigate artificial evolution, developmental processes must ...
Developmental artificial neural networks for shape recognition: a model of the retina
(University of Hertfordshire, 1996)
There has been recent interest in mimicking the self-organising processes of biological development to design artificial neural networks. An a priori decision must however be made as to the degree of biological detail ...
HARP: a statically scheduled multiple-instruction-issue architecture and its compiler
(University of Hertfordshire, 1994)
This paper presents the results of an investigation into the performance of a new statically scheduled multiple-instruction-issue architecture and its compiler. HARP is a Long Instruction Word Architecture developed in ...
Using conditional execution to exploit instruction level concurrency
(University of Hertfordshire, 1994)
Multiple-instruction-issue processors seek to improve performance over scalar RISC processors by providing multiple pipelined functional units in order to fetch, decode and execute several instructions per cycle. The process ...
Static Instruction Scheduling for the HARP Multiple-Instruction-Issue Architecture
(1993)
HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ...
Addressing Mechanisms for VLIW and Superscalar Processors
(1993)
RISC processors employ simple addressing modes which allow memory addresses to be calculated in a single processor cycle. This paper demonstrates that VLIW and Superscalar processor performance can be improved by further ...
Static instruction scheduling for the HARP multiple-instruction-issue architecture
(University of Hertfordshire, 1992)
HARP is a new multiple-instruction-issue architecture developed at the University of Hertfordshire. This paper describes the essential features of the HARP machine model and presents two compile-time scheduling techniques, ...
iHARP a Multiple Instruction Issue Processor Chip Incorporating RISC and VLIW Design Features
(1992)
RISC (Reduced Instruction Set Computers) processors have established an impressive performance standard by executing one instruction in each processor cycle. More recently, VLIW (Very Long Instruction Word) and superscalar ...